Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors

Y. Wang (1) , Mukherjee Chhandak (1) , H. Rezgui (1) , M. Deng (1) , Jonas Müller (2) , S. Pelloquin (3, 4) , Guilhem Larrieu (2) , C. Maneux (1)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique
3 LAAS-NEO - Équipe Nano-ingénierie et intégration des oxydes métalliques et de leurs interfaces
4 LAAS - Laboratoire d'analyse et d'architecture des systèmes

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current–voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs. We then incorporated these effects into the SPICE-compatible VNWFET compact model and further investigated the behaviors of trapping and electrothermal effects in basic logic circuits based on the compact model simulation.

Domaines: Electronique; Technologies Émergeantes [cs.ET]; Micro et nanotechnologies/Microélectronique

Y. Wang, Mukherjee Chhandak, H. Rezgui, M. Deng, Jonas Müller, et al.. Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors. Solid-State Electronics, 2024, 211, pp.108805. ⟨10.1016/j.sse.2023.108805⟩. ⟨hal-04297709⟩